Application of 16 bit four channel analog-to-digital converter GX9253 to benchmark AD9253 in radar echo signal acquisition

In radar systems, echo signal acquisition enables target detection, positioning, and tracking. After the radar emits electromagnetic waves, key information such as target distance, velocity, and orientation is obtained by receiving the echo signals reflected by the target. The echo signal has three major characteristics: high-speed transient, weak low amplitude, and wide dynamic range. The acquisition of wide dynamic range can avoid signal saturation or loss.

The GXSC‘s four channel 16 bit 125MSPS analog-to-digital converter is a device designed specifically for ultra high speed and wideband signal acquisition. The GX9253 is an on-chip sampling and holding circuit that features low design cost, low power consumption, small size, and ease of use. Through optimized design, the GX9253 has a conversion rate of up to 125MSPS, achieving excellent dynamic performance and low power consumption in small-sized packaging applications. The GX9253 analog-to-digital converter achieves good performance with a 1.8V single power supply and LVPECL/CMOS/LVDS compatible sampling clock. For most applications, no additional references or driving devices are required.

The GX9253 has a built-in PLL that automatically increases the frequency based on the sampling clock for serial data output sampling clock. The output data sampling clock is used to receive serial output bits, and the frame clock output is used to mark the output data byte signal. Supporting single channel power failure, the GX9253 typically consumes less than 2mW when all channels are disabled. It includes multiple features to improve flexibility and reduce system costs, such as programmable output clock, data alignment, and digital test mode. The available digital testing modes include built-in deterministic mode and pseudo-random mode, as well as custom testing mode input through serial interface (SPI).

Main features of GX9253:

Four channel low-power high-speed pipeline ADC with internal clock buffer and reference

Data rate: 20Msps~125Msps

Signal to Noise Ratio (SNR): 77.9dBFs@Vref =1V,fin=10MHz； seventy-two point two dBFs@Vref =1V,fin=200MHz

Stray free signal input range (SFDR): 96.66dBFs@Vref =1V,fin=10MHz； 78.8dBFs@Vref =1V,fin=10MHz

1.8V power consumption: single channel 170mW@125Msps

Built in benchmark and clock buffer

Analog input bandwidth 650MHz

2Vpp input voltage range, supporting up to 2.6Vpp

Power supply range: Analog power supply 1.7V to 1.9V; Digital power supply 1.7V to 1.9V

Differential Non Linear (DNL)=± 0.7LSB; Integral nonlinear INL=± 3.5LSB

Flexible power-off and standby modes, independent controllability of each channel, flexible output code value mode, support for multi chip synchronization, clock division