GXSC Analog-to-Digital Converter Replaces EV10AQ190A in Satellite Digital Receivers

Satellite digital receivers serve as the front end between satellite payloads and ground receiving systems, precisely converting the weak analog RF/IF signals received by the antenna into digital signals for subsequent demodulation, decoding, and data processing. Modern satellite communications typically employ multi-carrier, high-order modulation, and wideband spectrum transmission. Conventional commercial high-speed analog-to-digital converters often suffer from insufficient sampling rates and limited bandwidth, making them incapable of handling wideband satellite signals.

This article primarily introduces a GXSC four-channel 10-bit 1.25/2.5/5 GSPS high-speed analog-to-digital converter. It employs a proprietary design architecture that achieves excellent dynamic performance with a low power consumption of less than 3.2W. It is a pin-to-pin replacement for the EV10AQ190A in satellite digital receivers. The chip is specifically designed for high-end broadband communications and aerospace applications, featuring flexible interleaved sampling, wide input bandwidth, excellent dynamic performance, and space-grade reliability, fully meeting the performance requirements of satellite digital receivers.

The GXSC ADC integrates four 10-bit, 1.25 GSPS high-speed ADCs. Each channel has an independent DDR data clock; when multiple channels are active, any data clock can be selected to simultaneously acquire data from several channels. The chip supports interleaved operation between channels. In two-channel mode, the ADC operates at a sampling rate of 2.5 GSPS, while in single-channel mode, it operates at 5 GSPS. The chip supports AutoSync functionality, enabling cascading of multiple chips. It supports automatic synchronization for cascading multiple ADCs on a single board as well as across multiple boards.

GXSC Analog-to-Digital Converter Product Advantages:

 Features a proprietary architecture that achieves excellent dynamic performance with low power consumption of less than 3.2W

 Package dimensions are compatible with reference models, supporting functional replacement of the EV10AQ190A

 Utilizes an EBGA380 package with an operating temperature range of -55°C to +125°C

 Low-power optimized design, consuming 56% of the power of comparable models, with no heat sink required

Supports multi-chip automatic synchronization and provides dedicated acquisition IP for easy application

Full-power bandwidth: 3.0 GHz

Data latency: 80 master clock cycles

Static performance: DNL: -1.0/+1.1 LSB, INL: -1.3/+2.6 LSB

 Dynamic performance in 4-channel/2-channel/single-channel modes

-fs=1.25 GSPS, fin=620 MHz/1200 MHz

ENOB=7.98 bits, SFDR=62.30 dBFS, SNDR=49.82 dBFS

ENOB=7.83 bits, SFDR=60.71 dBFS, SNDR=48.87 dBFS

-fs=2.5 GSPS, fin=620 MHz/1200 MHz

ENOB=7.85 bits, SFDR=59.25 dBFS, SNDR=48.99 dBFS

ENOB=7.79 bits, SFDR=58.76 dBFS, SNDR=48.66 dBFS

-fs=5.0 GSPS, fin=620 MHz/1200 MHz

ENOB=7.73 bits, SFDR=59.50 dBFS, SNDR=48.29 dBFS

ENOB=7.59 bits, SFDR=55.96 dBFS, SNDR=47.47 dBFS

The data output format of the GXSC ADC can be programmed to either offset binary code or two’s complement format, offering users flexibility in selection. The product uses a parallel LVDS interface for data output, with a minimum conversion latency of 19 ns.