Phased-array radar and electronic warfare systems can utilize the GXSC analog-to-digital converter/clock jitter eliminator as a replacement for the AD9689/LMK04828.

The primary functions of phased-array radar and electronic warfare systems—including target detection, tracking, and identification, as well as electromagnetic countermeasures, signal interception, and jamming suppression—all rely on the efficient coordination of “signal reception–clock synchronization -analog-to-digital conversion-digital processing." These systems require rapid sampling of wide-band signals, high-resolution target identification, and multi-beam synchronous control, which depend on the ADC’s high sampling rate, wide input bandwidth, and high linearity, as well as the clock system’s low jitter and high synchronization.

Electronic warfare systems must perform weak signal interception, rapid jamming identification, and real-time jamming suppression amidst dense electromagnetic signals. This requires ADCs with high dynamic range and fast signal detection capabilities, as well as clock systems with ultra-low jitter and flexible timing configuration capabilities.

GXSC analog-to-digital converters offer advantages such as wide input bandwidth, high sampling rates, excellent linearity, small package size, and low power consumption. The dual-channel ADC core employs a multi-stage pipelined architecture and integrates on-chip digital calibration algorithms. Each ADC features a wide-bandwidth input and supports various user-selectable input ranges. An integrated reference voltage source simplifies design complexity. Analog inputs and clock signals are differential inputs, and several features are available to simplify automatic gain control (AGC) in communication receivers. A programmable threshold detector allows monitoring of incoming signal power using the fast detection control bit in the ADC registers.

The GXSC’s high-performance clock regulator supports JEDEC JESD204B; when using the device and SYSREF clocks, the 14 clock outputs of PLL2 can be configured to drive seven JESD204B converters or other logic devices. SYSREF can be provided via DC or AC coupling and is not limited to JESD204B applications; all 14 outputs can be individually configured as traditional high-performance clock system outputs. This chip is used in electronic countermeasures and features high performance, low power consumption, dual VCOs, dynamic digital delay, and signal loss retention, making it an ideal choice for providing flexible, high-performance clock trees.

The stability and reliability of the GXSC clock jitter eliminator are evident in every aspect. It is fully compatible with TI’s LMK04828, uses an SPI interface for communication, and is well-suited for embedded systems and FPGA-controlled board designs. It can be widely applied in high-speed data acquisition boards, electronic countermeasures, satellite communications, high-precision timing systems, and wireless communications, providing your system with exceptional performance and a reliable clock solution.