Application of GXSC Analog-to-Digital Converter Replacing AD9245 in Software-Defined Radio

Software-Defined Radio (SDR) is a technology that implements wireless communication functions through software-controlled hardware platforms. Its architecture comprises an RF front-end, high-speed analog-to-digital converters, and digital processing units. By digitizing RF front-end signals and leveraging software algorithms for multi-mode demodulation, wideband adaptation, and signal processing, SDR has become a critical technology in wireless communications, military electronics, and test and measurement fields.

The analog-to-digital converter (ADC) serves as the pivotal hub for converting analog to digital signals. GXSC‘s single-channel 14-bit 80MSPS ADC, manufactured using CMOS technology, is designed to rival ADI‘s AD9245. This chip‘s wide bandwidth, exceptional dynamic performance, and low power consumption perfectly balance the performance, cost, and integration demands of SDR systems, making it the preferred digital solution for mid-to-high-end SDR systems.

GXSC‘s ADC incorporates a high-performance sample-and-hold amplifier and voltage reference. The device employs a differential multi-stage pipeline architecture with output error correction logic to deliver 14-bit precision and guarantee no missing codes across the full temperature range. The wideband fully differential SHA supports multiple selectable input ranges and wide input common-mode voltages, including single-ended applications. It is suitable for multiplexing systems switching full-scale voltage levels across continuous channels, as well as sampling single-channel inputs at frequencies well above the Nyquist rate.

In wireless communication scenarios, SDR received signals are often accompanied by strong spurious interference and multipath fading, where weak useful signals are easily masked. This requires the ADC to possess high signal-to-noise ratio and wide dynamic range. The GXSC ADC supports multiple selectable rates including 20MSPS, 40MSPS, 65MSPS, and 80MSPS, with the following performance specifications:

• Static Performance: DNL: 0.5/+0.5 LSB, INL: 0.20/+0.20 LSB

• Differential Analog Input Bandwidth: 500 MHz

• Dynamic Performance:

- fin=5 MHz, ENOB=11.3 bits, SNDR=70.0 dB, SNR=71.0 dB

- fin=70MHz, ENOB=11.1 bits, SNDR=69.0dB, SNR=69.5dB

- fin=100MHz, ENOB=10.7 bits, SNDR=66.5dB, SNR=67.0dB

• Low power consumption: 210mW@80MSPS

• Input signal swing: 1Vpp-2Vpp

• Offset binary or two‘s complement data format

• On-chip integrated clock duty cycle stabilization circuit

• Flexible power-saving dropout mode