Replacing AD9245 with GX9254 Single-Channel 14-Bit 80MSPS ADC in Medical Imaging Equipment

Medical ultrasound imaging features non-invasiveness, no radiation, real-time imaging, and low cost. The high-frequency echo signals from the equipment are amplified, filtered, and digitized before being reconstructed into ultrasound tomographic images. The resolution and contrast of the images depend directly on the performance of the echo signal acquisition front end. Because ultrasound echo signals are characterized by high frequency, wide dynamic range, and transient pulses, this article introduces the GX9254 single-channel 14-bit 80MSPS analog-to-digital converter as a replacement for the AD9245 in medical imaging.

The key advantage of the GX9254 lies in its combination of high sampling rate and wide analog bandwidth: the 80MSPS sampling rate can directly perform bandpass sampling on ultrasound RF echoes up to 15MHz, enabling I/Q decomposition in the digital domain without analog quadrature demodulation, thus simplifying the front-end analog circuit design. The chip integrates a sample-and-hold amplifier and a reference source, requiring only a few decoupling capacitors externally for operation, resulting in a simple design. The parallel CMOS output interface connects directly to an FPGA, with low data transmission latency, facilitating real-time beamforming processing.

The GX9254‘s wideband fully differential SHA allows for multiple selectable input ranges and wide input common mode, including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels, as well as for sampling single-channel inputs at frequencies well above the Nyquist rate. Its product advantages are as follows:

Packaged in plastic QFN32, compatible with the imported product AD9245.

Single channel 20MSPS/40MSPS/65MSPS/80MSPS

Integrated on-chip voltage reference and sample-and-hold circuit

Low power consumption: 210mW@80MSPS

Input signal swing: 1Vpp-2Vpp

Offset binary or two‘s complement data format

On-chip integrated clock duty cycle stabilizer circuit

Flexible power-saving power-down mode

Static performance: DNL: 0.5/+0.5LSB, INL: 02.0/+2.0LSB

Differential analog input bandwidth: 500MHz

Dynamic performance:

fin=5MHz, ENOB=11.3Bit, SNDR=70.0dB, SNR=71.0dB

fin=70MHz, ENOB=11.1Bit, SNDR=69.0dB, SNR=69.5dB

fin=100MHz, ENOB=10.7Bit, SNDR=66.5dB, SNR=67.0dB