The analog-to-digital converter GX9245, benchmarked against the AD9245, is applied in IF sampling communication receivers

The intermediate frequency (IF) sampling communication receiver is a device designed for receiving, demodulating, and extracting data from IF signals. By directly sampling the IF signal, it simplifies the hardware architecture while minimizing signal loss and noise introduction. The analog-to-digital converter (ADC) within this device requires high-speed sampling, a wide dynamic range, and low-noise acquisition. The single-channel 14-bit 80 MSPS ADC, GX9245 from GXSC, is specifically designed for IF sampling. Its core features align perfectly with the "high-speed, precision, and integration" requirements of IF sampling communication receivers.

The GX9245 is a monolithic, single-supply, 14-bit analog-to-digital converter manufactured using CMOS technology. The device incorporates a high-performance sample-and-hold amplifier and voltage reference, employing a differential multi-stage pipelined architecture with output error correction logic to achieve 14-bit accuracy and ensure no missing codes across the full temperature range. The broadband fully differential SHA supports multiple selectable input ranges and wide input common-mode voltages, including single-ended applications.

The GX9245 is also highly suitable for multiplexed systems that switch full-scale voltage levels in continuous channels, as well as for sampling single-channel inputs at frequencies significantly above the Nyquist rate. The single-ended clock input of the GX9245 controls all internal conversion cycles, while the duty cycle stability circuit (DCS) compensates for variations in clock duty cycle while maintaining excellent overall ADC performance. The digital output data is represented in offset binary or two‘s complement format. The overrange (OTR) signal indicates input overflow conditions and, in conjunction with the most significant bit, determines whether it is a low or high overflow.

Product Advantages of GX9245:

Single-channel 20MSPS/40MSPS/65MSPS/80MSPS

Integrated on-chip voltage reference source and sample-and-hold circuit

Low power consumption: 210mW@80MSPS

Input signal swing: 1Vpp-2Vpp

Offset binary or two‘s complement data format

On-chip integrated clock duty cycle stabilization circuit

Flexible energy-saving power-off mode

Static Performance: DNL: 0.5/+0.5 LSB, INL: 0.2/+2.0 LSB

Differential analog input bandwidth: 500MHz

Dynamic Performance:  

- Fin=5MHz, ENOB=11.3Bit, SNDR=70.0dB, SNR=71.0dB

-fin=70MHz,ENOB=11.1Bit,SNDR=69.0dB,SNR=69.5dB

-fin=100MHz,ENOB=10.7Bit,SNDR=66.5dB,SNR=67.0dB