GXSC High-Speed Analog-to-Digital Converter Replaces ADC12D1800 for LiDAR Applications

LiDAR achieves three-dimensional modeling and precise ranging of target environments by emitting laser beams and receiving reflected signals. The sensing accuracy and response speed of LiDAR directly depend on the performance of echo signal acquisition and conversion—laser echo signals are not only weak and short in duration but also accompanied by significant noise interference, requiring analog-to-digital conversion devices to achieve relatively high sampling rates, resolution, and dynamic performance.

The GXSC dual-channel 12-bit 1.8GSPS high-speed ADC product adopts a self-developed architecture, enabling pin-to-pin replacement with the ADC12D1800. It achieves excellent dynamic performance with a low power consumption of less than 2.4W. This device integrates two 12-bit, 1.8GSPS high-speed ADCs, each with independent DDR data clocks (DCLKI and DCLKQ). When both channels operate, DCLKI and DCLKQ remain in-phase, allowing the use of just one clock to sample all channels. Additionally, it supports the AutoSync function for automatic synchronization, enabling multi-chip cascading. The product also supports both single-board multi-ADC cascading synchronization and multi-board multi-ADC cascading synchronization.

The data output format of the GXSC analog-to-digital converter can be programmed as offset binary code or two‘s complement binary code, allowing users to choose and utilize the desired format. The product employs a parallel LVDS interface for data output, with a minimum conversion delay of 18ns. The data interface supports both Demux mode and Non-Demux mode. In Demux mode, two sets of 12-bit LVDS buses output data in parallel, reducing the data rate of each LVDS bus by half to accommodate more data receiving devices.

Product advantages:

Encapsulation size compatible with reference model, supports pin-to-pin replacement for ADC12D1800

Encapsulated as plastic BGA292, with a working temperature range of -55°C to +105°C

Low-power optimized design, approximately 54% of the reference model, no need for a heat sink

Shorter conversion waiting time, saving approximately 20% compared to the reference model

The power-on calibration time is approximately 1% of the reference model, reducing the waiting time by 99%

A wider operating temperature range with excellent environmental adaptability

Supports automatic synchronization of multiple chips, provides dedicated acquisition IP for convenient application

Full power bandwidth: 3.0 GHz

Data delay: 28 master clock cycles

Static Performance: DNL: -0.9/+1.5 LSB, INL: -2.3/+2.8 LSB