GXSC high-speed ADC compatible with ADC12D1800 for consumer RF applications

The main applications of consumer radio frequency include mobile communication: supporting wireless communication for smartphones and other mobile devices; Automotive Electronics: Integrated cellular network, Wi Fi, and GNSS connectivity to support in car entertainment and remote information processing; Internet of Things: in fields such as smart homes and wearable devices.

These RF signals cannot be digitized without the signal processing of analog-to-digital converters. This article introduces a GXSC dual channel 12 bit 1.8GSPS high-speed ADC applied to consumer RF. This chip fully meets the broadband digitalization needs of consumer RF devices and provides a cost-effective and highly integrated solution for high-end consumer electronics RF links.

The RF digital link of consumer RF devices needs to achieve efficient capture and conversion of multi band, broadband analog signals, meeting the requirements of signal integrity for high-definition audio and video, high-speed data transmission, and adapting to the design constraints of miniaturization, low power consumption, and low cost of consumer electronics. The GXSC ADC adopts a self-designed architecture, with two built-in 12 bit 1.8GSPS high-speed ADCs and a full power bandwidth of 3.0GHz for broadband high-speed sampling, covering the entire frequency range of consumer RF.

Each channel ADC of the chip has an independent DDR data clock (DCLKI and DCLKQ). When both channel ADCs are working, DCLKI and DCLKQ are always in phase, so only one can be used to collect all channels. Supports AutoSync automatic synchronization function and can be used for cascading multiple chips. Support automatic synchronization of multiple ADCs cascaded on a single board and multiple ADCs cascaded on multiple boards.

Product advantages:

Package size compatible with reference models, supporting Pin To Pin substitution for ADC12D1800

Low power optimized design, approximately 54% of the reference model, without the need for a heat sink

Shorter conversion waiting time, saving about 20% compared to the reference model

The power on calibration time is about 1% of the reference model, reducing waiting time by 99%

Wide working temperature range, good environmental adaptability

Support automatic synchronization of multiple chips, provide dedicated collection IP, convenient for application

Excellent dynamic performance was achieved with low power consumption below 2.4W.

Power bandwidth: 3.0GHz

Data latency: 28 master clock cycles

Static performance: DNL: -0.9/+1.5LSB, INL: -2.3/+2.8LSB

Dynamic performance (fs=1.8GSPS, input signal power -1dBFS)

-fin=248MHz； ENOB=8.7Bit，SFDR=64.7dBFS，SNR=54.1dBFS

-fin=498MHz； ENOB=8.5Bit，SFDR=64.8dBFS，SNR=52.8dBFS

-fin=1147MHz； ENOB=7.9Bit，SFDR=60.1dBFS，SNR=49.4dBFS

-fin=1448MHz； ENOB=7.7Bit，SFDR=59.3dBFS，SNR=48.5dBFS