Replacement of the AD9633 with the GXSC A/D Converter for Multi-Channel Ultrasound Front-End Echo Signal Acquisition

Medical ultrasound imaging technology offers advantages such as radiation-free operation, strong real-time capabilities, and controllable costs, making it a vital diagnostic and health screening tool. The process involves transmitting ultrasound waves through a transducer; these waves penetrate human tissue and generate echo signals. The front-end acquisition system captures these echo signals and performs analog-to-digital conversion. Following this, the signals undergo beamforming and signal processing in the back-end to ultimately generate clear images.

For the front-end echo signal acquisition in this ultrasound equipment, the GXSC four-channel 12-bit 125 MSPS analog-to-digital converter (ADC) can be used. This chip is a four-channel 12-bit high-speed ADC specifically designed for multi-channel high-speed acquisition scenarios, based on a highly efficient architecture. It features built-in on-chip sample-and-hold circuits and operates on a single 1.8V power supply. With core characteristics such as low power consumption, compact size, high dynamic range, and flexible interfaces, it is deeply optimized to meet the demands of multi-channel front-end echo signal acquisition in ultrasound applications, providing a precise and efficient signal acquisition solution for ultrasound imaging.

The GXSC ADC’s four-channel synchronous sampling capability ensures that echo signals from different probe elements are acquired simultaneously, providing an accurate phase foundation for beamforming; its high dynamic range and low-noise characteristics ensure that faint echo signals are accurately reproduced, preventing signal distortion; and the LVDS high-speed interface enables efficient digital signal transmission, reducing data loss and improving signal processing efficiency. Furthermore, the single-supply power consumption and high integration of this domestically produced A/D converter significantly simplify the hardware design of the acquisition chain, reducing system power consumption and size.

The chip includes several features designed to maximize flexibility and minimize system costs, such as programmable output clock and data alignment, as well as digital test pattern generation. Available digital test patterns include built-in deterministic and pseudorandom patterns, as well as custom user-defined test patterns input via the Serial Peripheral Interface (SPI). Its key features are as follows:

• 1.8V power supply operation

• Low power consumption: 100 mW per channel at 125 MSPS, with scalable power supply options

• SNR = 71 dB (to Nyquist)

• SFDR = 91 dBc (at Nyquist)

• DNL = +0.3 LSB (typical); INL = +0.5 LSB (typical)

• Serial LVDS (ANSI-644 by default) with low-power and reduced-signal options

• 650 MHz full-power analog bandwidth

• 2 Vp-p input voltage range