GXSC ADC Replaces AD9633 in Diversified RF Receivers

Modern RF receiver systems have gradually evolved from single-band, fixed-bandwidth designs to diversified architectures featuring multi-band, wide-bandwidth, multi-channel synchronous reception, and lightweight integration. Unlike traditional single-frequency, fixed-point receivers, these systems adopt a universal architecture comprising a broadband RF front end, multi-channel synchronous digitization, and a back-end digital demodulator, enabling the reception of RF signals across multiple bands and standards.

The workflow is as follows: the antenna receives spatial RF signals, which are then low-noise amplified, filtered, and downconverted to intermediate frequency (IF) signals via mixing. A high-speed ADC then digitizes the analog IF signals, and finally, an FPGA/DSP performs digital filtering, channel selection, demodulation, spectrum analysis, and signal recognition. This article primarily introduces the application of a GXSC four-channel 12-bit 125 MSPS analog-to-digital converter as a replacement for the AD9633 in a versatile RF receiver, overcoming the limitations of traditional RF equipment such as limited functionality, insufficient accuracy, and poor consistency.

The GXSC ADC features an on-chip sample-and-hold circuit, designed to deliver low cost, low power consumption, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for applications where small package size is critical, delivering excellent dynamic performance and low power consumption. The chip requires a single 1.8V power supply and an LVPECL/CMOS/LVDS-compatible sampling clock to operate at full performance. In many applications, no external reference or driver components are required.

The GXSC ADC includes several features designed to maximize flexibility and minimize system cost, such as programmable output clock and data alignment, as well as digital test pattern generation. Available digital test patterns include built-in deterministic and pseudorandom patterns, as well as custom user-defined test patterns input via the serial port interface (SPI). Its key features are as follows:

• 1.8V power supply operation

• Low power consumption: 100 mW per channel at 125 MSPS, with scalable power supply options

• SNR = 71 dB (to Nyquist)

• SFDR = 91 dBc (to Nyquist)

• DNL = +0.3 LSB (typical); INL = +0.5 LSB (typical)

• Serial LVDS (ANSI-644 by default) with low-power and reduced-signal options

• 650 MHz full-power analog bandwidth