GXSC ADC Replaces AD9680 in Ultra-Wideband Satellite Receivers

Ultra-wideband satellite receivers are front-end devices in satellite communication systems responsible for tasks such as receiving broadband RF signals, capturing weak carriers, analyzing multi-frequency signals, and demodulating low-spurious data. The ultra-wideband RF signals received by the satellite antenna undergo low-noise amplification, image rejection filtering, and multi-stage down-conversion before being converted into broadband analog intermediate-frequency (IF) signals, which are then fed into a high-speed ADC for analog-to-digital conversion. The digitized broadband signals undergo digital down-conversion, filtering and decimation, carrier synchronization, and demodulation and decoding to ultimately reconstruct the transmitted satellite data, voice, and image information.

The GXSC ADC can replace the AD9680 for data acquisition in ultra-wideband satellite receiver solutions. It meets the requirements for wide input bandwidth, high sampling rates, and low power consumption, providing engineers with powerful signal processing capabilities.

The GXSC ADC supports sampling of broadband analog signals up to 2 GHz, meeting the high-frequency sampling requirements of multimode digital receivers. Its dual-channel ADC core, featuring a multi-stage, differential pipelined architecture combined with on-chip buffers and sample-and-hold circuits, ensures high sampling rates and excellent linearity. Additionally, the chip integrates a reference voltage source, simplifying the design process and reducing the need for external components.

Each ADC channel of the chip is connected to two digital downconverters (DDCs), with each DDC containing up to five cascaded signal processing stages, including a 12-bit numerically controlled oscillator (NCO) and four half-band decimation filters. This design effectively reduces the data rate while supporting the complex signal processing requirements of multi-band receivers. The flexibility of the DDC modules allows engineers to configure them according to specific application needs, optimizing the signal processing workflow.

The GXSC ADC features are as follows:

JESD204B (Subclass 1) encoded serial digital output

Total power consumption per channel at 1 GSPS: 1.65 W (default settings)

SFDR = 85 dBFS (340 MHz), 80 dBFS (1 GHz)

SNR = 65.3 dBFS at 340 MHz, AIN = −1.0 dBFS; 60.5 dBFS at 1 GHz, AIN = −1.0 dBFS

ENOB = 10.8 bits (10 MHz)

DNL = ±0.5 LSB

INL = ±2.5 LSB

Noise density = −154 dBFS/Hz (1 GSPS)

DC Power Supplies: 1.25 V, 2.5 V, and 3.3 V

Internal ADC Reference Voltage Source

2 GHz Full-Power Analog Input Bandwidth

95 dB Channel Isolation/Crosstalk

Amplitude Detection Bits Support Efficient AGC

Differential Clock Input

Integer Clock Divider Ratios: 1, 2, 4, or 8

Flexible JESD204B Channel Configuration